Power Efficient 3D Clock Distribution Network Design with TSV Count Optimization

Low Power Clock Network Design

Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanc...

Clock Distribution Network Optimization under Self-Heating and Timing Constraints

Reduced Power Flip Flop Design for Clock Distribution Networks

In this paper a technique is proposed to reduce the power consumption in clock distribution networks. Power has become a major issue in most VLSI designs. Power distribution in VLSI differs from product to product. However it is interesting to note that clock system and logic part itself consume most of total chip power. In practise a large portion of clock distribution network (CDN)s and flip ...

TSV-Based 3D Integration

Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose plac...

Low Power Clock Distribution Schemes in VLSI Design

This paper reviewed the comparison between different clock distribution schemes which used for low power VLSI design which are the most important aspect in the industry. The main clock distribution schemes are single driver clock scheme and distributed buffers clock scheme. There are different tradeoffs in both the techniques such as size of buffers, number of buffers etc.